Circuit diagram:

25 Watt Amplifier

Parts:

R1,R4 = 47K	1/4W Resistors
R2 = 4K7	1/4W Resistors
R3 = 1K5	1/4W Resistors
R5 = 390R	1/4W Resistors
R6 = 470R	1/4W Resistors
R7 = 33K	1/4W Resistors
R8 = 150K	1/4W Resistors
R9 = 15K	1/4W Resistors
R10 = 27R	1/4W Resistors
R11 = 500R	1/2W Trimmer Cermet
R12,R13,R16 = 10R	1/4W Resistors
R14,R15 = 220R	1/4W Resistors
R17 = 8R2	2W Resistor
R18 = R22	4W Resistor (wirewound)

C1 = 470nF	63V Polyester Capacitor
C2 = 330pF	63V Polystyrene Capacitor
C3,C5 = 470΅F	63V Electrolytic Capacitors
C4,C6,C8,C11 = 100nF	63V Polyester Capacitors
C7 = 100΅F	25V Electrolytic Capacitor
C9 = 10pF	63V Polystyrene Capacitor
C10 = 1΅F	63V Polyester Capacitor

Q1-Q5 = BC560C	45V100mA Low noise High gain PNP Transistors
Q6 = BD140	80V 1.5A PNP Transistor
Q7 = BD139	80V 1.5A NPN Transistor
Q8 = IRF532	100V 12A N-Channel Hexfet Transistor
Q9 = IRF9532	100V 10A P-Channel Hexfet Transistor

Power supply circuit diagram:

Power supply

Parts:

R1 = 3K3	1/2W Resistor

C1 = 10nF	1000V Polyester Capacitor
C2,C3 = 4700΅F	50V Electrolytic Capacitors
C4,C5 = 100nF	63V Polyester Capacitors

D1	200V 8A Diode bridge
D2	5mm. Red LED
F1,F2	3.15A Fuses with sockets

T1	220V Primary, 25 + 25V Secondary 120VA Mains transformer

PL1	Male Mains plug

SW1	SPST Mains switch

Notes:

Can be directly connected to CD players, tuners and tape recorders. Simply add a 10K Log potentiometer (dual gang for stereo) and a switch to cope with the various sources you need.
Q6 & Q7 must have a small U-shaped heatsink.
Q8 & Q9 must be mounted on heatsink.
Adjust R11 to set quiescent current at 100mA (best measured with an Avo-meter in series with Q8 Drain) with no input signal.
A correct grounding is very important to eliminate hum and ground loops. Connect in the same point the ground sides of R1, R4, R9, C3 to C8. Connect C11 at output ground. Then connect separately the input and output grounds at power supply ground.

Technical data:

Output power: well in excess of 25Watt RMS @ 8 Ohm (1KHz sinewave)

Sensitivity: 200mV input for 25W output

Frequency response: 30Hz to 20KHz -1dB

Total harmonic distortion @ 1KHz: 0.1W 0.014% 1W 0.006% 10W 0.006% 20W 0.007% 25W 0.01%
Total harmonic distortion @10KHz: 0.1W 0.024% 1W 0.016% 10W 0.02% 20W 0.045% 25W 0.07%

Unconditionally stable on capacitive loads

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MOSFET amplifier

Assume in the circuit above V_T$" align="middle" border="0" height="35" width="132"> and the transistor is in saturation region, i.e., V_{in}-V_T$" align="middle" border="0" height="35" width="131">, then we have

$\begin{displaymath}\left\{ \begin{array}{l} I_{DS}=K(V_{in}-V_T)^2 \\ V_{out}=V_{DS}=V_{dd}-I_{DS} R=V_{dd}-KR(V_{in}-V_T)^2 \end{array} \right. \end{displaymath}$

The second equation relates the output $V_{out}$ to the input $V_{in}$ , as shown by the red segment of the curve in the plot above. As the transistor is in saturation region,

$\begin{displaymath}V_{out}=V_{dd}-KR(V_{in}-V_T)^2\ge V_{in}-V_T \end{displaymath}$

which can be solved for $V_{in}$ to get:

$\begin{displaymath}V_{in}<\frac{-1+\sqrt{1+4KRV_{dd}}}{2KR}+V_T \end{displaymath}$

It can be seen that when the transistor is in saturation mode the slope of the curve (red) indicates the ratio between input $V_{in}$ and output $V_{out}$ . And the voltage gain of the circuit is defined as:

$\begin{displaymath}g=\frac{d V_{out}}{d V_{in}}=\frac{d}{d V_{in}}(V_{dd}-K(V_{in}-V_T)^2 R) =-2KR(V_{in}-V_T) \end{displaymath}$

Example: Assume $V_{dd}=10V$ , $R=10 k\Omega$ , $K=0.5\;mA/V^2$ , . For the transistor to be in saturation region, we need

V_T=1\;V$" align="middle" border="0" height="35" width="130">
$V_{in}<[-1+\sqrt{1+4KRV_{dd}}\;]/2KR+V_T=2.32\;V$

then we have

$\begin{displaymath}V_{out}=V_{dd}-K(V_{in}-V_T)^2 R=10-5(V_{in}-1)^2 \end{displaymath}$

and the voltage gain is a function of the input $V_{in}$ :

$\begin{displaymath}g(V_{in})=\frac{d}{d V_{in}} V_{out}(V_{in})=-10(V_{in}-1) \end{displaymath}$

This nonlinear equation can be represented by the table below:

$V_{in}$	0	1	1.4	1.5	1.8	1.9	2.0	2.1	2.2	2.3	2.32	2.35	2.4
$V_{out}$	10	10	9.2	8.8	6.8	6.0	5.0	4.0	2.8	1.6	1.3	0.9	0.0

In particular, when the input $V_{in}$ increases from

, the output $V_{out}$ decreases from

, with a gain $g(V_{in})=g(1.8)=-10(1.8-1)=-8$ . Also when the input $V_{in}$ increases from

, the output $V_{out}$ decreases from

, with a gain $g(V_{in})=g(2)=-10(2-1)=-10$ .

In summary, we see that

When the transistor is in saturation mode, the circuit behaves as a voltage amplifier.
The voltage gain is the slope of the tangent of the curve (red) as a function of $V_{in}$ .
The value of the gain depends on the level of input $V_{in}$ . When $V_{out}(V_{in})$ is negative.
When , the transistor is cutoff. On the other hand, when 2.32V$" align="middle" border="0" height="35" width="102">, is more than one below , for example, , . If the bias voltage is , the input voltage varies between 1.4V and 1.6V. The output voltage can be found to be:

$\begin{displaymath}v_{out}=V_{dd}-RI_{DS}=V_{dd}-RK(V_{in}-V_T)^2=5-10 (V_{in}-1)^2 \end{displaymath}$

In particular, corresponding to , the output voltage and the current are, respectively, , and , as shown in the figure below:

Biasing: In the example above, the DC offset of the input is at 1.5V, so that the transistor is working in the saturation region when the magnitude of the AC input is limited. However, if this offset is either too high or too low, the gate voltage may go beyond the saturation region to enter either the triode or the cutoff region. In either case, the output voltage will be severely distorted, as shown below:

It is therefore clear that the DC offset or biasing gate voltage has to be properly setup to make sure the dynamic range of the input signal is within the saturation region.
Method 1: One way to provide the desired DC offset is to use two resistors and that form a voltage divider, as shown in the figure below (a). As the input resistance of a MOSFET transistor is very high, therefore the gate of the transistor does not draw any current, the DC offset voltage can simply obtained as:

$\begin{displaymath}V_{bias}=V_{dd}\frac{R_1}{R_1+R_2} \end{displaymath}$

The input AC signal through the input capacitor is then superimposed on this DC offset.

Method 2: Another way to set up the bias is the circuit shown in (b) above. Assume , , , $V_{dd}=10V$ , and . The bias voltage can be found to be $V_B=V_{bias}=1.6V$ , and the voltage between gate and source is $V_{GS}=V_B-V_{in}$ . The output voltage is

$\begin{displaymath}V_{out}=V_{dd}-R_d K (V_{GS}-V_T)^2=V_{dd}-R_d K (V_B-V_{in}-V_T)^2=10-10\times (0.6-V_{in})^2 \end{displaymath}$

When , .
To determine the dynamic range of the input $V_{in}$ , recall the conditions for the transistor to be in saturation region:
- To avoid cutoff region: $V_{GS}-V_T \ge 0$ . For this particular circuit,
  $\begin{displaymath}V_{GS}-V_T=V_B-V_{in}-V_T=0.6-V_{in} \ge 0 \end{displaymath}$
  
  Solving this we get $V_{in} \le 0.6V$ with corresponding output $V_{out} < 10V$ .
- To avoid triode region: $V_{DS} \ge V_{GS}-V_T$ . For this particular circuit,
  $\begin{displaymath}V_{DS}=V_{out}-V_{in}=(V_{dd}-R_dI_{DS})-V_{in} =V_{dd}-R_dK (V_B-V_{in}-V_T)^2-V_{in} \ge V_B-V_{in}-V_T \end{displaymath}$
  
  that is
  $\begin{displaymath}V_{out}=V_{dd}-R_dK (V_B-V_{in}-V_T)^2 \ge V_B-V_T \end{displaymath}$
  
  i.e.,
  $\begin{displaymath}V_{out}=10-10\times (0.6-V_{in})^2 \ge 0.6 \end{displaymath}$
  
  Solving this for $V_{in}$ we get $V_{in} \ge -0.37V$ , with corresponding output $V_{out} \ge 0.6V$
Therefore the overall dynamic range for the input is
$\begin{displaymath}-0.37V \le V_{in} \le 0.6V \end{displaymath}$

with the corresponding output range
$\begin{displaymath}0.6V \le V_{out} \le 10V \end{displaymath}$

and the overall voltage gain is about . Note that the output voltage is in phase with the input voltage.
Source Follower: If the output is taken from the source, instead of the drain of the transistor, the circuit is called a source follower.

Assume $R_S=10 k\Omega$ , and . To find the input and output voltages and the gain of the circuit, consider the current $I_{DS}=V_{out}/R_S$ :

$\begin{displaymath}I_{DS}=K(V_{GS}-V_T)^2=K(V_{in}-V_{out}-V_T)^2=V_{out}/R_S \end{displaymath}$

Plugging in the given values, we get
$\begin{displaymath}(V_{in}-V_{out}-1)^2=V_{out} \end{displaymath}$

If , this equation becomes:
$\begin{displaymath}(V_{out}-1)^2=V_{out} \end{displaymath}$

which can be solved to get or . We take the smaller voltage in order for the transistor to be outside the cutoff region:
V_T=1 \end{displaymath}" border="0" height="31" width="303">

Similarly, if , the equation becomes:
$\begin{displaymath}(V_{out}-2)^2=V_{out} \end{displaymath}$

and we get . The voltage gain of the source follower is
$\begin{displaymath}g=\frac{\Delta V_{out}}{\Delta V_{in}}=\frac{1-0.4}{3-2}=0.6<1 \end{displaymath}$